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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? complete timing solution in a small outline package ? 8khz, 1.544mhz, 2.048mhz or 19.44mhz input reference frequencies ? 8khz (frame pulse), 2.048mhz, 8.192mhz, 16.384mhz, 19.44mhz and two 155.52mhz (lvpecl) output clock frequencies ? low intrinsic jitter and wander generation ? automatic holdover modes ? holdover and lock indication ? selectable operation modes ? accepts reference inputs from two independent sources ? 3.3v supply voltage applications ? sdh add/drop multiplexers ? next gen. digital loop carriers ? atm edge switches ? line cards description the ZL30462 is a timing module, which functions as a complete system clock solution for general timing applications. the ZL30462 has been designed around zarlink's digital and analog phase locked loop (dpll and apll) technology and can lock to one of two inputs that can be derived from two independent sources. the inputs automatically detect if one of four frequencies is present, 8khz, 1.544mhz, 2.048mhz or 19.44mhz. the module has three jitter attenuated output clocks one 19.44mhz (cmos) and two 155.52mhz (lvpecl). in addition to these outputs the module also supplies an 8khz frame pulse plus 2.048mhz, 8.192mhz and 16.384mhz clocks. november 2003 ordering information ZL30462mcf 40 smtdil 0 c to +70 c ZL30462 compact timing module data sheet figure 1 - functional block diagram reference select mux pri sec tie corrector circuit control state machine dpll input im prairment monitor output interface circuit apll converter rsel lock /tclr master oscillator osc holdover ms1 ms2 /reset ja155p/n-1 ja19mo lk1 (19.44mhz) /f16o tvdd tgnd vdd agnd c2o lk2 c8o /c16o ja155p/n-2
ZL30462 data sheet 2 zarlink semiconductor inc. figure 2 - 40 pin smt dil top view pin description table pin number name description 1c16o clock 16.384mhz (cmos output). this general purpose output may be used for st-bus operation with a 16.384mhz clock. 2c8o clock 8.192mhz (cmos output). this general purpose output may be used for st-bus operation at 8.192mb/s. 3c2o clock 2.048mhz (cmos output). this general purpose output may be used for st-bus operation at 2.048mb/s. 4 f16o frame pulse st-bus 16.384mb/s (cmos output). this is an 8khz 61ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 16.384mb/s. 5lk1 (19.44mhz) link1. connect this pin to pin 6. this 19.44mhz signal must not be used for external applications. 6lk2 link2. connect this pin to pin 5. 7 agnd1 ground. 8nc no connection. this pin is unused and has no internal connection. 9nc no connection. this pin is unused and has no internal connection. 10 agnd1 ground. 11 12 ja155n-2 ja155p-2 ja 155-2 clock (lvpecl output) . this differential output provides a low jitter 155.52mhz clock. 12 ic internal connection. do not connect to this pin. 13 v dd2 positive power supply. 3.3v 14 lock lock indicator (cmos output). this output goes high when the pll is frequency locked to the input reference. 40 1 20 21 1
ZL30462 data sheet 3 zarlink semiconductor inc. 15 ja19mo clock 19.44mhz (cmos output). this output provides a low jitter 19.44mhz clock. 16 17 ja155n-1 ja155p-1 ja 155-1 clock (lvpecl output) . this differential output provides a low jitter 155.52mhz clock. 18 agnd2 ground. 19 v dd3 positive power supply. 3.3v 20 agnd1 ground. 21 tv dd oscillator positive power supply. 3.3v 22 tgnd oscillator ground. 23 osc oscillator master clock (cmos output). this pin can be used to monitor the output of the on-board master oscillator. 24 v dd1 positive power supply. 3.3v 25 pri primary reference (input). this input is a primary reference source for synchronization. the module can synchronize to falling edge of the following reference clocks: 8khz, 1.544mhz, 2.048mhz or the rising edge of 19.44mhz. this pin is selected when a logic 0 is applied to the rsel input pin. this pin is internally pulled up to v dd . 26 sec secondary reference (input). this input is a secondary reference source for synchronization. the module can synchronize to falling edge of the following reference clocks: 8khz, 1.544mhz, 2.048mhz or the rising edge of 19.44mhz. this pin is selected when a logic 1 is applied to the rsel input pin. this pin is internally pulled up to v dd . 27 ic internal connection. do not connect to this pin. 28 tclr tie circuit reset (input). a high to low transition at this input initiates phase realignment between the input reference and the generated output clocks. this pin is internally pulled to gnd. 29 reset reset (input). logic 0 will forces the module into a reset state. this pin must be held to logic 0 for a minimum of 1s to reset the module properly. the module must be reset after power-up. 30 agnd1 ground. 31 ic internal connection. do not connect to this pin. 32 nc no connection. this pin is unused and has no internal connection. 33 nc no connection. this pin is unused and has no internal connection. 34 rsel reference source select (input). a logic low selects the pri (primary) reference source as the input reference signal and a logic high selects the sec (secondary) input. this pin is internally pulled down to gnd. see table 1. 35 ms1 mode/control select 1 (input). this input, in conjunction with ms2, determines the state (normal, holdover or freerun) of operation. see table 2. 36 ms2 mode/control select 2 (input). this input, in conjunction with ms1, determines the state (normal, holdover or freerun) of operation. see table 2. 37 nc no connection. this pin is unused and has no internal connection. pin description table (continued) pin number name description
ZL30462 data sheet 4 zarlink semiconductor inc. 1.0 functional description the ZL30462 offers a complete timing solution in a 1.2? x 1? module package. the module comprises three main components, a dpll which performs the main operational functions, an apll which provides three low jitter output clocks and an on-board master oscillator. figure 1 shows a functional block diagram of the module, which is described in the following sections. 1.1 reference select mux circuit the ZL30462 accepts two simultaneous reference input signals which can be derived from independent sources. both reference inputs will automatically accept one of four frequencies, 8khz, 1.544mhz, 2.048mhz or 19.44mhz. the 8khz, 1.544mhz and 2.048mhz input clocks are all triggered on the falling edge and the 19.44mhz is triggered on the rising edge. the primary reference (pri) signal or the secondary reference (sec) signal can be selected by simply using the rsel pin, see table 1. 1.2 time interval error (tie) corrector circuit when the ZL30462 finishes locking to a reference an arbitrary phase difference will remain between its output clocks and its reference; this phase difference is part of the normal operation of the ZL30462. if so desired, the output clocks can be brought into phase alignment with the pll reference by using the tclr control pin. using tclr if the ZL30462 is locked to a reference, then the output clocks can be brought into phase alignment with the pll reference by using the tclr control pin according to the procedure below: ? wait until the ZL30462 lock indicator is high, indicating that it is locked ? pull tclr low ? hold tclr low for 250 s for 1.544 mhz, 2.048 mhz or 19.44 mhz, or 10 sec for 8 khz (input frequency). ? pull tclr high this sequence re-initiates the ZL30462 locking procedure; the lock indicator will go low 5 sec after tclr is pulled low and will remain low for 10 sec. 38 holdover holdover (cmos output). this output goes to a logic high whenever the pll goes into holdover mode. 39 nc no connection. this pin is unused and has no internal connection. 40 v dd positive power supply. 3.3v rsel input reference 0pri 1 sec table 1 - input reference selection pin description table (continued) pin number name description
ZL30462 data sheet 5 zarlink semiconductor inc. 1.3 core pll the most critical element of the ZL30462 is the core pll. this generates a phase-locked clock filters wander and suppresses input phase transients.the core pll supports three mandatory modes of operation: free-run, normal (locked) and holdover. each of these modes places specific requirements on the building blocks of the core pll. ? in free-run mode, the core pll locks to the 20mhz master clock oscillator (osc). the stability of the generated clock remains the same as the stability of the master clock oscillator. ? in normal mode, the core pll locks to one of the input reference clocks. both inputs provide preprocessed phase data to the core pll including detection of reference clock quality. this preprocessing reduces the load on the core pll and improves quality of the generated clock. ? in holdover mode, the core pll generates a clock based on data collected from past reference signals. the core pll enters holdover mode if the selected reference input is lost, or under external hardware control. table 2 shows how each of these modes can be selected via the external hardware pins ms1 and ms2. table 2 - operating modes within the dpll there are a number of key components, which include a phase detector, limiter, loop filter, digitally controlled oscillator, clock synthersizer and lock indicator. 1.3.1 phase detector the phase detector compares the virtual reference signal from the tie corrector circuit, with its internal input frequency select circuit and provides an error signal corresponding to the phase difference between the two. this error signal is passed to the limiter circuit. 1.3.2 limiter the limiter receives the error signal from the phase detector and ensures that the dpll responds to all input transient conditions with a maximum output phase slope of 41ns per 1.326ms. 1.3.3 loop filter in normal mode, the clocks generated by the ZL30462 are phase-locked to the input reference signal. the dpll loop filter is similar to a first order low pass filter with a 1.5 hz cutoff frequency for all four reference frequency selections (8khz, 1.544mhz, 2.048mhz or 19.44mhz). this filter ensures that the wander transfer requirements in ets 300 011 and at&t tr62411 are met. 1.3.4 digitally controlled oscillator (dco) the dco receives the limited and filtered signal from the loop filter, and based on its value, generates a corresponding digital output signal. the synchronization method of the dco is dependent on the state of the ZL30462. ms2 ms1 mode of operation 0 0 normal mode 0 1 holdover mode 1 0 freerun mode 11reserved
ZL30462 data sheet 6 zarlink semiconductor inc. in normal mode, the dco provides an output signal which is frequency and phase locked to the selected input reference signal. in holdover mode, the dco is free running at a frequency equal to the last (30ms to 60ms) frequency the dco was generating while in normal mode. in freerun mode, the dco is free running with an accuracy equal to the accuracy of the osc 20mhz source. 1.3.5 clock synthesizer the output of the dco is connected to the clock synthesizer that generates the output clocks and frame pulse. ? c2o: 2.048mhz clock with nominal 50% duty cycle ? c8o: 8.192mhz clock with nominal 50% duty cycle ? c16o : 16.384mhz clock with nominal 50% duty cycle ?f16o : 8khz frequency, with 61ns wide, logic low frame pulse in addition to the above, lk1 also generates a 19.44mhz clock, which is linked externally to lk2. this clock drives the apll stage which generates the low jitter 19.44mhz and 155.52mhz clock outputs (see section 1.4). lk1: 19.44mhz clock with nominal 50% duty cycle 1.3.6 lock indicator (lock) the ZL30462 is considered locked (lock=1) when the residual phase movement after declaring locked condition does not exceed 20 ns; as required by standard wander generation mtie and tdev tests. to ensure the integrity of the lock status indication, the ZL30462 holds the lock pin low for a minimum of 10 sec. 1.4 jitter attenuator the ZL30462 output driver circuit provides two lvpecl jitter attenuated outputs at 155.52mhz and one cmos output at 19.44mhz. there are no external components or adjustments required to support this part of the circuit, as the loop filter and additional power supply decoupling circuitry has been built into the module. the on-board loop filter has been optimized to ensure the quality of the jitter attenuated output. but to maintain the quality of these outputs it is extremely important that they are terminated correctly and the track impedance is 50 ohms. failure to do so will affect the modules performance will affect the quality of these clocks. figure 3 shows one method of terminating one of the lvpecl outputs, further termination information can be found in the ZL30462 applications note. the input to the apll stage can be isolated from the dpll, by removing the link connection between lk1 (pin 5) and lk2 (pin 6), this may be useful for product verification or test purposes.
ZL30462 data sheet 7 zarlink semiconductor inc. figure 3 - lvpecl output termination circuit 1.5 input impairment monitor this circuit monitors both the input reference signals and reports their status automatically to the dpll. this block automatically enables the holdover mode (auto-holdover) when the selected reference is outside the auto- holdover capture range. (see ac electrical characteristics - performance). this includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. when the incoming signal returns to normal, the dpll is returned to normal mode with the output signal locked to the input signal. the holdover output signal in the ZL30462 is based on the incoming signal 30ms minimum to 60ms prior to entering the holdover mode. the amount of phase drift while in holdover is negligible because the holdover mode is very accurate (e.g., <0.01ppm, relative to the master oscillator frequency). consequently, the phase delay between the input and output after switching back to normal mode is preserved. 1.6 control state machine the ZL30462 control state machine supporting the three mandatory clock modes required by any network element that operates in a synchronous network. the simplified version of this state machine is shown in figure 4 and includes the mandatory states: free-run, normal and holdover. these states are complemented by two additional states: reset and auto holdover, which are critical to the ZL30462 operation under the changing external conditions. these clock modes determine the behavior of a network element to the unforeseen changes in the network synchronization hierarchy. requirements for clock modes are defined in the international standards e.g.: g.812, g.813, gr-1244-core and gr-253-core and they are very strictly enforced by network operators. figure 4 also shows how the control input pins - rsel, ms1, ms2 and reset interact with the control state machine. lvpecl driver lvpecl receiver = 50? = 50? vcc note : vcc = +3.3v 127? 127? 82.5? 82.5? output driver
ZL30462 data sheet 8 zarlink semiconductor inc. figure 4 - ZL30462 state machine 1.6.1 reset state in this state, the dpll clocks are stopped and all functions are initialized. the reset state is entered by pulling the reset pin to logic 0 for a minimum of 1s. when the reset pin is pulled back to logic 1, internal logic starts a 625s initialization process before switching into the free-run state (ms2, ms1 = 10). it is recommended that a module reset is performed immediately after power up, to ensure the ZL30462 is set to a know state. the reset function would normally be under the control of the system or host controller, usually in the form of a microprocessor or fpga. alternatively, figure 5 shows how to connect a simple hardware reset circuit to the ZL30462. figure 5 - simple reset circuit normal (locked) 00 auto holdover holdover 01 freerun 10 reset ms2, ms1 == 01 or rsel change ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 != 10 ______ reset == 1 ms2, ms1 == 10 forces unconditional return from any state to freerun rsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr 0 --> 1 {manual} notes: 0 --> 1 : transition from 0 to 1 &= : and operation != : not equal == : equal {auto} : automatic transition auto holdover: automatic holdover state ms2, ms1 {manual} : manual transition {ahrd} : automatic holdover {mhr} : manual holdover ______ reset ZL30462 r 10k rp 1k c 10nf vdd
ZL30462 data sheet 9 zarlink semiconductor inc. 1.6.2 free-run state the free-run state is entered when synchronization to the network is not required or is not possible. typically this occurs during installation, repairs or when a network element operates as a master node in an isolated network. in the free-run state, the accuracy of the generated clocks is determined by the accuracy and stability of the ZL30462 master crystal oscillator. when powering up the equipment, it is recommended that the module has at least 2 hours to stabilize after the equipment has reached its normal operating temperature. 1.6.3 normal state (locked state) the normal state is entered when normal mode is selected and a good quality reference clock is available. the ZL30462 automatically detects the frequency of the reference clock (8khz, 1.544mhz, 2.048mhz or 19.44mhz) and sets the lock status pin to logic 1 after acquiring synchronization. in the normal state all generated clocks (c2o, c8o, c16o , ja19mo, ja155p/n-1 and ja155p/n-2) and frame pulse (f16o ) are derived from network timing. to guarantee uninterrupted synchronization, the ZL30462 continuously monitors the quality of both input reference clocks. this dual architecture enables quick replacement of a poor or failed reference and minimizes the time spent in other states. during this state the ZL30462 can tolerate a 17ppm/s frequency change (on the active input) without generating an alarm or changing state. 1.6.4 holdover state the holdover state is typically entered for short durations while network synchronization is temporarily disrupted. in holdover mode, the ZL30462 generated clocks are not locked to an external reference signal, but these outputs are based on stored coefficients in memory. these coefficients are determined while the module is in normal state for at least 10 minute after the modules stabilization period.? the initial frequency offset of the ZL30462?s dpll in holdover mode is 1x10 -10 . once the ZL30462 has transitioned into holdover mode, holdover stability is determined by the stability of the 20mhz master clock oscillator (osc pin), which is a 20ppm crystal oscillator. 1.6.5 auto holdover state the auto holdover state is a transitional state that the ZL30462 enters automatically when the active reference fails unexpectedly. when the ZL30462 detects loss of reference it waits in auto holdover state until the failed reference recovers. the holdover status pin may be used to alert the system controller about the failure and in response the controller may switch to the secondary reference clock. the holdover pin indicates when you are in either auto holdover and holdover states. if the selected input fails (or becomes invalid for any reason) the ZL30462 will transition into auto-holdover. if the system controller then elects to switch to the other input and that input is also invalid, then the ZL30462 will remain in auto holdover until that input becomes valid. this is an internal protection system, to ensure that the module does not use an invalid reference. if the ZL30462 is reset at any time (e.g. during power-up) and mode select pins are trying to force the module to lock to an invalid input (ms1, ms2 == 00) the module will transition into auto holdover and the holdover pin will be asserted. because the reset function clears the ZL30462?s memory, then there will be no holdover history. in this case, even though the output status pin is showing that the module is in holdover, the output clock accuracy will default to that of freerun mode. so to summarise the above, i n a typical network element application, the ZL30462 will typically operate in normal mode (ms2, ms1 == 00) generating synchronous clocks. the state machine is designed to perform some transitions automatically, leaving other, less time dependent tasks to the system controller. the state machine includes two stimulus signals which are critical to automatic operation: ?ok --> fail? and ?fail --> ok? that represent loss (and recovery) of the reference signal or its drift by more than 30000 ppm. their transitions force
ZL30462 data sheet 10 zarlink semiconductor inc. the dpll to move into and out of the auto holdover state. the ZL30462 state machine may also be driven by controlling the mode select pins ms2, ms1. to avoid network synchronization problems, the state machine has built-in basic protection that does not allow switching the dpll into a state where it cannot operate correctly e.g. it is not possible to force the dpll into normal mode when all references are lost. 2.0 applications this section details how to control and monitor the hardware pins of the ZL30462 and general power supply decoupling information. more detailed application information can be found in the ZL30462 applications note. 2.1 ZL30462 mode switching - examples the ZL30462 is designed to transition from one mode to the other driven by the internal state machine or by manual control. the following examples present a couple of typical scenarios of how the ZL30462 can be employed in network synchronization equipment (e.g. timing modules, line cards or stand alone synchronizers). 2.1.1 system start-up sequence: free-run --> holdover --> normal the free-run to holdover to normal transition represents a sequence of steps that will most likely occur during a new system installation or scheduled maintenance of timing cards. the process starts from the reset state and then transitions to free-run when the device is being initialized. at the end of this process the ZL30462 should be switched into normal mode (with ms2, ms1 set to 00) instead of holdover mode. if the reference clock is available, the ZL30462 will transition briefly into holdover state to acquire synchronization and switch automatically to normal state. if the reference clock is not available the ZL30462 will stay in holdover state indefinitely. whilst in holdover state, the dpll will continue generating clocks with the same accuracy as in the free-run mode, waiting for a valid reference clock. when the system is connected to the network (or timing card switched to a valid reference) this will enable the dpll to start the synchronization process. after acquiring lock, the ZL30462 will automatically switch from holdover state to normal state without system intervention. this transition to the normal state will be flagged by the lock status pin. figure 6 - transition from free-run to normal mode normal (locked) 00 auto holdover holdover 01 freerun 10 reset ms2, ms1 == 01 or rsel change ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 != 10 ______ reset == 1 ms2, ms1 == 10 forces unconditional return from any state to freerun rsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr 0 --> 1 {manual}
ZL30462 data sheet 11 zarlink semiconductor inc. 2.1.2 single reference operation: normal --> auto holdover --> normal the normal to auto-holdover to normal transition will usually happen when the network element loses its single reference clock unexpectedly or when it has two references but switching to the secondary reference is not a desirable option. the sequence starts with the unexpected failure of a reference signal shown as transition ok --> fail in figure 7 at a time when ZL30462 operates in normal mode. this failure is detected at the active input based on the following fail criteria: ? frequency offset on 8khz, 1.544mhz, 2.048mhz and 19.44mhz reference clocks exceeds 30000 ppm (3%). ? phase hit on 1.544mhz, 2.048mhz and 19.44mhz exceeds half of the cycle of the reference clock. after detecting any of these anomalies on a reference clock the control state machine will force the dpll to automatically switch into the auto holdover state. this condition is flagged by lock = 0 and holdover = 1. figure 7 - automatic entry into auto holdover state and recovery into normal mode the ZL30462 will automatically return to the normal state after the reference signal recovers from failure. this transition is shown on the state diagram as a fail --> ok change. this change becomes effective when the reference is restored and there have been no phase hits detected for at least 64 clock cycles. this transition from auto holdover to normal state is performed as ?hitless? reference switching. 2.1.3 dual reference operation: normal --> auto holdover --> holdover --> normal the normal to auto-holdover to holdover to normal sequence represents the most likely operation of ZL30462 in network equipment. the sequence starts from the normal state and transitions to auto holdover state due to an unforeseen loss of reference. the failure conditions triggering this transition were described in section 2.1.2. when in the auto holdover state, the ZL30462 can return to normal state automatically if the lost reference is restored. if the reference clock failure persists for a period of time that exceeds the system design limit, the system control processor may initiate a reference switch. if the secondary reference is available the ZL30462 will briefly switch into holdover state and then transition to normal state. normal (locked) 00 auto holdover holdover 01 freerun 10 reset ms2, ms1 == 01 or rsel change ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 != 10 ______ reset == 1 ms2, ms1 == 10 forces unconditional return from any state to freerun rsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr 0 --> 1 {manual} automatic return to normal: ahdr=0 or manual return to normal: ahrd=1 & mhr 0--> 1
ZL30462 data sheet 12 zarlink semiconductor inc. figure 8 - entry into auto holdover state and recovery into normal mode by switching references the new reference clock will most likely have a different phase but it may also have a different fractional frequency offset. to lock to a new reference with a different frequency, the dpll will step gradually towards the new frequency. the frequency slope will be limited to less than 2.0 ppm/sec. 2.1.4 reference switching (refsel): normal --> holdover --> normal the normal to holdover to normal sequence switching can be performed at any time. an example of this could be during routine maintenance or an upgrade of equipment, where the active input references is going to be affected. so, changing the input reference under controlled conditions should avoid any unnecessary chances of generating a phase hit. figure 9 - manual reference switching normal (locked) 00 auto holdover holdover 01 freerun 10 reset ms2, ms1 == 01 or rsel change ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 != 10 ______ reset == 1 ms2, ms1 == 10 forces unconditional return from any state to freerun rsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr 0 --> 1 {manual} ahrd=0 (automatic return enabled) normal (locked) 00 auto holdover holdover 01 freerun 10 reset ms2, ms1 == 01 or rsel change ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 != 10 ______ reset == 1 ms2, ms1 == 10 forces unconditional return from any state to freerun rsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr 0 --> 1 {manual}
ZL30462 data sheet 13 zarlink semiconductor inc. two types of transitions are possible: ? semi-automatic transition, which involves changing the rsel input to select the other reference clock, without changing the mode select inputs ms2, ms1 = 00 (normal mode). this forces ZL30462 to momentarily transition through the holdover state and automatically return to normal state after synchronizing to the other reference clock. ? manual transition, which involves switching into holdover mode (ms2, ms1 = 01), changing references with rsel, and manual return to the normal mode (ms2, ms1 = 00). in both cases, the change of references provides ?hitless? switching. 2.2 power supply decoupling figure 10 shows the recommended power supply decoupling requirements of the ZL30462. the ZL30462 does have a level of internal decoupling components built in to the module, but to ensure optimum performance these external components are required. figure 10 - power supply decoupling ZL30462 vdd2 vdd tvdd vdd1 tgnd agnd1 3.3v l1 c2 c1 l1 & l2 : 10h c2 & c5 : 10f c1, c3, c4, c6 - c9 : 100nf l2 c5 c4 c3 vdd3 c6 c7 c8 c9 agnd1 agnd1 agnd2
ZL30462 data sheet 14 zarlink semiconductor inc. 3.0 characteristics 3.1 ac and dc electrical characteristics * voltages are with respect to ground (gnd) unless otherwise stated * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * voltages are with respect to ground (gnd) unless otherwise stated * voltages are with respect to ground (gnd) unless otherwise stated note 1: rise and fall times are measured at 20% and 80% levels. absolute maximum ratings* parameter symbol min max units 1 supply voltages v dd tv dd -0.3 -0.3 5.0 5.0 v v 2 input voltage v in -0.05 v dd +0.5 v recommended operating conditions* parameter symbol min typ max units 1 supply voltages v dd tv dd 3.0 3.3 3.6 v 2 operating temperature t a 025 70 o c dc electrical characteristics* characteristics symbol min typ max units test conditions 1 supply current i dd 325 450 ma output unloaded 2 supply current ti dd 5 10 ma output unloaded 3 cmos: high-level input voltage v ih 0.7v dd v 4 cmos: low-level input voltage v il 00.3v dd v 5 cmos: input leakage current i il 15 a vi=v dd or gnd 6 cmos: high-level output voltage v oh 2.4 v i oh = 8ma 7 cmos: low-level output voltage v ol 0.4 v i ol = 8ma 8 lvpecl: differential output voltage |v od | 480 600 720 mvp z t =100 ohms 9 lvpecl: high-level output voltage v oh v dd -0.9 v z t =100 ohms 10 lvpecl: low-level output voltage v ol v dd -1.5 v 11 lvpecl: output rise and fall times t rf 250 300 700 ps note 1
ZL30462 data sheet 15 zarlink semiconductor inc. * voltages are with respect to ground (gnd) unless otherwise stated note 2: the freerun accuracy is directly related to the accuracy of the master oscillator note 3: the dpll holdover accuracy is also affected by the holdover stability of the master oscillator note 4: this figure is offset by the accuracy of the master oscillator * voltages are with respect to ground (gnd) unless otherwise stated figure 11 - timing parameters measurement voltage levels ac electrical characteristics* parameter symbol min max units test conditions 1 freerun mode accuracy f a -20 20 ppm note 2 2 holdover mode accuracy f a -0.01 f a +0.01 ppm note 3 3 lock range f a -104 f a +104 ppm note 4 4 wander generation w gen itu-t g.813 option1 5 wander transfer w tr itu-t g.813 option1 6 phase response to input signal interruptions p tt itu-t g.813 option1 7 phase transients p t itu-t g.813 option1 8 holdover entry phase transients h ept itu-t g.813 option1 9lock time l t 30 s ac electrical characteristics* - timing parameter measurements - cmos voltage levels* characteristics symbol typical units 1 threshold voltage v t 0.5v dd v 2 rise and fall threshold voltage high v hm 0.7v dd v 3 rise and fall threshold voltage low v lm 0.3v dd v timing reference points all signals v hm v t v lm t ir, t or t if, t of
ZL30462 data sheet 16 zarlink semiconductor inc. figure 12 - input to output timing (normal mode) ac electrical characteristics - input phase alignment characteristics symbol min max units test conditions 1 8khz ref. pulse width high t r8h 100 ns 2 8khz ref. input to f16o delay t r8d 43 61 ns 3 1.544mhz ref. pulse width high t r1.5h 100 ns 4 1.544mhz ref. input to f16o delay t r1.5d 360 393 ns 5 2.048mhz ref. pulse width high t r2h 100 ns 6 2.048mhz ref. input to f16o delay t r2d 252 288 ns 7 19.44mhz ref. pulse width high t r19h 23 ns 8 19.44mhz ref. input to f16o delay t r19d 30 51 ns 9 reference input rise and fall time t ir , t if 10 ns t v t v t v t v t v tc = 125s tc = 51.44ns tc = 488.28ns tc = 647.67ns tc = 125s pri/sec 8khz pri/sec 1.544mhz pri/sec 2.048mhz pri/sec 19.44mhz /f16o r8h t r8d t r1.5h t r1.5d t r2h t r2d t r19d t r19h t
ZL30462 data sheet 17 zarlink semiconductor inc. figure 13 - input control signal setup and hold time ac electrical characteristics - input control signals characteristics symbol min max units test conditions 1 input controls setup time t s 100 ns 2 input controls hold time t h 100 ns ac electrical characteristics - outputs timing characteristics symbol min max units test conditions 1 f16o to ja19mo delay t j19d -35 -25 ns 4 f16o to c16o delay t c16d -35 -25 ns 5 f16o to c8o delay t c8d -35 -25 ns 6 f16o to c2o delay t c2d -35 -25 ns /f16o ms1, ms2, rsel, t v t v s t h t
ZL30462 data sheet 18 zarlink semiconductor inc. figure 14 - output timing t v t v tc = 51.44ns tc = 61.035ns tc = 125s /f16o ja19mo /c16o c8o c2o tc = 122.07ns tc = 488.28ns t v t v t v j19d t c16d t c8d t c2d t
ZL30462 data sheet 19 zarlink semiconductor inc. 3.2 performance characteristics * supply voltage and operating temperature are as per recommended operating conditions * supply voltage and operating temperature are as per recommended operating conditions performance characteristics: measured output jitter - gr-253-core and t1.105.03 conformance* telcordia gr-253-core and ansi t1.105.03 jitter generation requirements ZL30462 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes ja155p/n clock output 1oc-12 622.08 mbit/s 12khz to 5mhz (category ii) 0.1 ui pp 161 24.2 ps p-p 1.905 ps rms ja19mo clock output 2oc-3 155.54 mbit/s 65khz to 1.3mhz 0.15 ui pp 964 283.1 ps p-p 22.89 ps rms 3 12khz to 1.3mhz (category ii) 0.1 ui pp 643 209.4 ps p-p 16.49 ps rms performance characteristics: measured output jitter - g.732, g.735 to g.739 conformance* itu-t g.732, g.735, g.736, g.737, g.738, g739 jitter generation requirements ZL30462 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes c16o , c8 and c2 clock outputs 1e1 2048 kbits/s 20hz to 100khz 0.05 ui pp 24.4 1.26 ns p-p
ZL30462 data sheet 20 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions performance characteristics: measured output jitter - g.813 conformance - option 1 itu-t g.813 jitter generation requirements ZL30462 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes ja155p/n clock output 1stm-4 622.08 mbit/s 250khz to 5mhz 0.1 ui pp 161 11.9 ps p-p 0.94 ps rms ja19mo clock output 2stm-1 155.54 mbit/s 65khz to 1.3mhz 0.1 ui pp 643 283.1 ps p-p 22.89 ps rms c16o , c8o and c2o clock output 3e1 2048 kbit/s 20hz to 100khz 0.05 ui pp 24.4 1.26 ns p-p performance characteristics: measured output jitter - g.813 conformance - option 2 itu-t g.813 jitter generation requirements ZL30462 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ units notes ja155p/n clock output 1stm-4 622.08 mbit/s 12khz to 5mhz 0.1 ui pp 161 24.2 ps p-p 1.905 ps rms ja19mo clock output 2stm-1 155.54 mbit/s 65khz to 1.3mhz 0.1 ui pp 643 283.1 ps p-p 22.89 ps rms
previous package codes package code acn date issue apprd. c zarlink semiconductor 2003 all rights reserved. 1 --- 15 oct 03
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